1. Field of the Invention
The invention generally relates to a memory cache and, more specifically, to techniques for storing ECC checkbits in a level 2 (L2) cache.
2. Description of the Related Art
Electrical and magnetic interference inside a computer system can cause bits of dynamic random access memory (DRAM) to spontaneously change states. Research has shown that many of these errors are caused by background radiation that can spontaneously change the contents of a memory cell. To manage these types of state changes and other errors associated with stored data, memory systems oftentimes include error-correcting capabilities.
Error-correcting capabilities come in many flavors. Some memory systems store a redundant parity bit that represents the parity of a byte or word (e.g., 32 bits) of data. The parity bit indicates whether the data includes an even or odd number of high-level bits, which can be checked against the data to indicate if a single bit error has occurred. Other memory systems include error-correcting code (ECC) memory that stores a parity bit and an error-correcting code, such as a single error-correcting, double error-detecting (SEC-DED) Hamming code. A SEC-DED Hamming code can correct a single bit error and detect (but not correct) a double bit error. Another type of ECC memory uses triple modular redundancy (TMR) hardware where three redundant systems store data, and the three systems implement a voting mechanism to protect against single event upsets of one copy of the data.
Error-correcting capabilities can be implemented on the memory chip (i.e., DIMM or dual inline memory module) or in the memory controller that interfaces with the memory chip. In the case where the error-correcting capabilities are implemented in the memory controller, the memory bandwidth may be burdened by repeated requests to read the ECC checkbits from the memory unit. For example, in one conventional implementation, 256 bits of data stored in the memory unit is associated with 16 bits of ECC checkbits. In such an implementation, for each request to read 256 bits of data, a separate request to read 16 bits of ECC checkbits is also required. Typically, the ECC checkbits are also read in widths equal to the memory bandwidth (e.g., 256 bits). Thus, for each request to read ECC checkbits associated with a particular row of data, the memory controller receives a plurality of ECC checkbits associated with other rows of data. Consequently, as many different rows of data are fetched from the memory unit, the same row of ECC checkbits may be fetched repeatedly, using a potentially significant portion of the available memory bandwidth.
Accordingly, what is needed in the art is a more effective approach for storing the ECC checkbits at the memory controller in order to reduce redundant read requests transmitted over the memory interface.